;---------------------------------------------------- ;Copyright (C), 2005-2008, lst. ;版权所有 (C), 2005-2008, lst. ;所属模块 CPU初始化 ;作者： lst ;版本： V1.0.0 ;初始版本完成日期：2009-02-05 ;文件描述 CPU初始化必须用汇编语言实现的部分 ;其他说明 无 ;修订历史 ;2. 日期 2010-01-04 ; 作者 lst ; 新版本号：V1.0.1 ; 修改说明 移植到keil MDK下，没有修改代码 ;1. 日期 2009-06-10 ; 作者 lst ; 新版本号：V1.0.0 ; 修改说明 s3c6410的原始版本 ;------------------------------------------------------ INCLUDE Option.inc USERMODE EQU 0x10 SYSMODE EQU 0x1f FIQMODE EQU 0x11 IRQMODE EQU 0x12 SVCMODE EQU 0x13 ABORTMODE EQU 0x17 UNDEFMODE EQU 0x1b MODEMASK EQU 0x1f NOINT EQU 0xc0 wtcon EQU 0x7e004000 ; Watch-dog timer mode Peripheral_base EQU 0x70000000 vic0_intenclear EQU 0x71200014 vic1_intenclear EQU 0x71200014 others EQU 0x7e00f900 R1_iA EQU (1<<31) R1_nF EQU (1<<30) R1_VE EQU (1<<24) R1_I EQU (1<<12) R1_BP EQU (1<<11) ; Z bit R1_C EQU (1<<2) R1_A EQU (1<<1) R1_M EQU (1<<0) apll_lock EQU 0x7e00f000 mpll_lock EQU 0x7e00f004 apll_con EQU 0x7e00f00c mpll_con EQU 0x7e00f010 epll_con0 EQU 0x7e00f014 epll_con1 EQU 0x7e00f018 clk_src EQU 0x7e00f01c clk_div0 EQU 0x7e00f020 clk_out EQU 0x7e00f02c mem_sys_cfg EQU 0x7e00f120 rst_stat EQU 0x7E00F904 inform0 EQU 0x7E00FA00 inform1 EQU 0x7E00FA04 inform2 EQU 0x7E00FA08 inform3 EQU 0x7E00FA0C vpwr_cfg EQU 0xB2A0F804 vsleep_cfg EQU 0xB2A0F818 vosc_stable EQU 0xB2A0F824 vpwr_stable EQU 0xB2A0F828 vrst_stat EQU 0xB2A0F904 vinform0 EQU 0xB2A0FA00 vinform1 EQU 0xB2A0FA04 vinform2 EQU 0xB2A0FA08 vinform3 EQU 0xB2A0FA0C EXPORT _start IMPORT srom_cs0_init ;初始化sram总线 IMPORT dram_init ;初始化dram总线 IMPORT |Image$$usr_stack$$ZI$$Limit| ;栈顶地址，在脚本中定义 IMPORT |Image$$svc_stack$$ZI$$Limit| ;栈顶地址，在脚本中定义 IMPORT |Image$$irq_stack$$ZI$$Limit| ;栈顶地址，在脚本中定义 IMPORT |Image$$fiq_stack$$ZI$$Limit| ;栈顶地址，在脚本中定义 IMPORT |Image$$undef_stack$$ZI$$Limit| ;栈顶地址，在脚本中定义 IMPORT |Image$$abort_stack$$ZI$$Limit| ;栈顶地址，在脚本中定义 PRESERVE8 AREA RESET, CODE, READONLY ENTRY _start b reset_start ; handlerReset b except_undef ; handlerUndef b except_swi ; SWI interrupt handler b except_pabort ; handlerPAbort b except_dabort ; handlerDAbort b . ; handlerReserved b . ; handlerIRQ b . ; fiq no use except_undef ; 未定义指令异常 b . except_swi ; SWI异常 b . except_pabort ; 取址异常 b . except_dabort ; 取数据异常 b . reset_start mrs r0,cpsr ;取CPSR bic r0,r0,#MODEMASK ;清模式位 orr r1,r0,#SVCMODE|NOINT ;设置为管理态，并禁止中断 msr cpsr_cxsf,r1 ;切换到管理态,可防止意外返回0地址时出错. ldr sp,=0xc002000 ;设置临时栈指针，主内存等设置好后，将改在主内存 mov r0, #0 mcr p15, 0, r0, c7, c7, 0 ; Invalidate Entire I&D Cache mrc p15, 0, r0, c1, c0, 0 orr r0, r0, #R1_I mcr p15, 0, r0, c1, c0, 0 ;Enable I Cache ; Peripheral Port Setup,Base Addres 0x70000000, Size 256 MB (0x13) ldr r0, =(Peripheral_base+0x13) mcr p15,0,r0,c15,c2,4 ; Interrupt Disable ldr r0, =vic0_intenclear ldr r1, =0xFFFFFFFF; str r1, [r0] ldr r0, =vic0_intenclear ldr r1, =0xFFFFFFFF; str r1, [r0] ldr r0, =wtcon ; Disable WatchDog Timer ldr r1, =0x0 str r1, [r0] ; Set to Synchronous Mode ldr r0, =others ldr r1, [r0] orr r1, r1, #0x40 ; SyncMUX = Sync str r1, [r0] nop nop nop nop nop ldr r1, [r0] orr r1, r1, #0x80 ; SyncReq = Sync str r1, [r0] WaitForSync ldr r1, [r0] ; Read OTHERS and r1, r1, #0xF00 ; Wait SYNCMODEACK = 0xF cmp r1, #0xF00 bne WaitForSync ; Check PLL and CLKDIV ldr r3, =0x83FF3F07 ; Mask for APLL_CON/MPLL_CON ldr r4, =0x80FF3F07 ; Mask for EPLL_CON0 ldr r5, =0x0000FFFF ; Mask for EPLL_CON1 ldr r6, =0x0003FF17 ; Mask for CLKDIV0 ldr r0, =apll_con ; Check APLL ldr r1, [r0] and r1, r1, r3 ldr r2, =((1<<31)+(apll_mdiv<<16)+(apll_pdiv<<8)+(apll_sdiv)) ; APLL_CON value to configure cmp r1, r2 bne PLL_NeedToConfigure ldr r0, =mpll_con ; Check MPLL ldr r1, [r0] and r1, r1, r3 ldr r2, =((1<<31)+(mpll_mdiv<<16)+(mpll_pdiv<<8)+(mpll_sdiv)) ; MPLL_CON value to configure cmp r1, r2 bne PLL_NeedToConfigure ldr r0, =epll_con0 ; Check EPLL_CON0 ldr r1, [r0] and r1, r1, r4 ldr r2, =((1<<31)+(epll_mdiv<<16)+(epll_pdiv<<8)+(epll_sdiv)) ; EPLL_CON0 value to configure cmp r1, r2 bne PLL_NeedToConfigure ldr r0, =epll_con1 ; Check EPLL_CON1 ldr r1, [r0] and r1, r1, r5 ldr r2, =epll_kdiv ; EPLL_CON1 value to configure cmp r1, r2 bne PLL_NeedToConfigure ldr r0, =clk_div0 ; Check CLKDIV0 ldr r1, [r0] and r1, r1, r6 ; CLKDIV0 value to configure ldr r2, =((pclk_div<<12)+(hclkx2_div<<9)+(hclk_div<<8)+(mpll_div<<4)+(apll_div<<0)) cmp r1, r2 bne CLKDIV_NeedToConfigure b PLL_CLKDIV_AlreadyConfigured ; APLL/MPLL/EPLL and CLKDIV0 is already configured PLL_NeedToConfigure ldr r0, =clk_src ldr r1, [r0] bic r1, r1, #0x7 ; select FIN out,Disable PLL Clock Out str r1, [r0] ldr r0, =clk_div0 ldr r1, [r0] bic r1, r1, #0xff00 bic r1, r1, #0xff ldr r2, = ((pclk_div<<12)+(hclkx2_div<<9)+(hclk_div<<8)+(mpll_div<<4)+(apll_div<<0)) orr r1, r1, r2 str r1, [r0] ; change PLL value ldr r1, =0x4B1 ; Lock Time 0x4b1 (100us ;Fin12MHz) for APLL/MPLL ldr r2, =0xE13 ; Lock Time 0xe13 (300us ;Fin12MHz) for EPLL ldr r0, =apll_lock str r1, [r0] ; APLL Lock Time str r1, [r0, #0x4] ; MPLL Lock Time str r2, [r0, #0x8] ; EPLL Lock Time ldr r0, =apll_con ldr r1, =((1<<31)+(apll_mdiv<<16)+(apll_pdiv<<8)+(apll_sdiv)) str r1, [r0] ldr r0, =mpll_con ldr r1, =((1<<31)+(mpll_mdiv<<16)+(mpll_pdiv<<8)+(mpll_sdiv)) str r1, [r0] ldr r0, =epll_con1 ldr r1, =epll_kdiv str r1, [r0] ldr r0, =epll_con0 ldr r1, =((1<<31)+(epll_mdiv<<16)+(epll_pdiv<<8)+(epll_sdiv)) str r1, [r0] ; Set System Clock Divider CLKDIV_NeedToConfigure ldr r0, =clk_div0 ldr r1, [r0] bic r1, r1, #0x30000 bic r1, r1, #0xff00 bic r1, r1, #0xff ldr r2, =((pclk_div<<12)+(hclkx2_div<<9)+(hclk_div<<8)+(mpll_div<<4)+(apll_div<<0)) orr r1, r1, r2 str r1, [r0] ; Enable PLL Clock Out ldr r0, =clk_src ldr r1, [r0] orr r1, r1, #0x7 ; PLL Clockout str r1, [r0] ; System will be waiting for PLL unlocked after this instruction PLL_CLKDIV_AlreadyConfigured bl srom_cs0_init bl dram_init ldr r0, =mem_sys_cfg ldr r1, [r0] orr r1,r1,#0x1000 ;set norflash bus_width = 16 bic r1, r1, #0xbf ;DDR Port132bit,cs0、1、4、5sromc，cs2、3nfcon str r1, [r0] mrc p15,0,r0,c1,c0,0 orr r0,r0,#R1_VE ; enable VIC mcr p15,0,r0,c1,c0,0 ;以下初始化L1页表，平板式全映射 ldr r0,=0x50000000 ;L1页表地址 mov r1,#0 ldr r3,=0xc12 ;不开cache loopnommu mov r2,r1,lsl #20 ;目标段编号写入L1条目的高12位 add r2,r2,r3 str r2,[r0],#4 add r1,r1,#1 cmp r1,#0x500 ;0~2fffffff不cache，不开写缓冲 bne loopnommu ldr r3,=0xc1e ;开cache loopmmu mov r2,r1,lsl #20 ;目标段编号写入L1条目的高12位 add r2,r2,r3 str r2,[r0],#4 add r1,r1,#1 cmp r1,#0x580 ;128M sdram区 bne loopmmu ldr r3,=0xc12 ;不开cache loopnommu1 mov r2,r1,lsl #20 ;目标段编号写入L1条目的高12位 add r2,r2,r3 str r2,[r0],#4 add r1,r1,#1 cmp r1,#0x1000 ;高端地址，不开cache bne loopnommu1 ldr r0,=0x50000000 mcr p15,0,r0,c2,c0,0 ;页表基地址 ldr r0,=0xffffffff ;全部域具有管理者权限 mcr p15,0,r0,c3,c0,0 ;写域寄存器 mrs r0,cpsr bic r0,r0,#MODEMASK orr r1,r0,#UNDEFMODE|NOINT msr cpsr_cxsf,r1 ; UndefMode ldr sp,=|Image$$undef_stack$$ZI$$Limit| orr r1,r0,#ABORTMODE|NOINT msr cpsr_cxsf,r1 ; AbortMode ldr sp,=|Image$$abort_stack$$ZI$$Limit| orr r1,r0,#IRQMODE|NOINT msr cpsr_cxsf,r1 ; IRQMode ldr sp,=|Image$$irq_stack$$ZI$$Limit| orr r1,r0,#FIQMODE|NOINT msr cpsr_cxsf,r1 ; FIQMode ldr sp,=|Image$$fiq_stack$$ZI$$Limit| orr r1,r0,#SVCMODE|NOINT msr cpsr_cxsf,r1 ; SVCMode ldr sp,=|Image$$svc_stack$$ZI$$Limit| orr r1,r0,#SYSMODE|NOINT msr cpsr_cxsf,r1 ; userMode ldr sp,=|Image$$usr_stack$$ZI$$Limit| IF :DEF:boot ldr r0,=0x3000405c mov pc,r0 ELSE IMPORT load_preload ; 加载程序，在C中定义 bl load_preload ENDIF ALIGN END