; cpu revision definition s3c6410 has evt0, evt1
evt0            EQU         36410100
evt1            EQU         36410101
cpu_revision    EQU         evt1        ;ʱÖÓÉèÖÃÊÇû¿¼ÂÇevt0£¬Ö»ÄÜÑ¡Ôñ evt1

; system clock definition
clk_133MHZ      EQU         133000000
clk_200MHZ      EQU         200000000
clk_266MHZ      EQU         266000000
clk_300MHZ      EQU         300000000
clk_400MHZ      EQU         400000000
clk_532MHZ      EQU         532000000
clk_666MHZ      EQU         666000000   ; async

eclk_96MHZ      EQU         96000000
eclk_84_7MHZ    EQU         84666667    ; for iis 44.1 khz
eclk_92MHZ      EQU         92160000    ; for iis 48 khz

syncmode        EQU         1

; change apll_clk definition
;apll_clk        EQU         clk_133MHZ        ; sync 133:133:66.5
;apll_clk        EQU         clk_200MHZ        ; sync 200:100:50
;apll_clk        EQU         clk_266MHZ        ; sync 266:133:66.5
;apll_clk        EQU         clk_300MHZ        ; sync 400:75:25
;apll_clk        EQU         clk_400MHZ        ; sync 400:100:50
apll_clk        EQU         clk_532MHZ        ; sync 532:133:66.5
;apll_clk        EQU         clk_666MHZ        ; sync 666:133.4:66.5

fin             EQU         12000000

; fout = mdiv*fin/(pdiv*2^sdiv)
; fvco = mdiv*fin/pdiv

; change eclk definition for epll fout
;eclk            EQU         eclk_96MHZ
eclk            EQU         eclk_84_7MHZ
;eclk            EQU         eclk_92MHZ

; set clock source : mpll, apll

; mpll setting,mclk use for asyncronous clk mode
mpll_mdiv       EQU         266       ; fvco=1064MHZ, fout=266MHZ
mpll_pdiv       EQU         3
mpll_sdiv       EQU         2
mpll_clk        EQU         (((fin>>mpll_sdiv)/mpll_pdiv)*mpll_mdiv)  ; mpll clock

; apll setting

    IF (apll_clk == clk_133MHZ)
apll_mdiv       EQU         133    ; fvco=532MHZ, fout=133MHZ
apll_pdiv       EQU         3
apll_sdiv       EQU         2
    ENDIF
    IF (apll_clk == clk_200MHZ)
apll_mdiv       EQU         200    ; fvco=800MHZ, fout=200MHZ
apll_pdiv       EQU         3
apll_sdiv       EQU         2
    ENDIF
    IF (apll_clk == clk_266MHZ)
apll_mdiv       EQU         266    ; fvco=1064MHZ, fout=266MHZ
apll_pdiv       EQU         3
apll_sdiv       EQU         2
    ENDIF
    IF (apll_clk == clk_300MHZ)
apll_mdiv       EQU         300    ; fvco=600MHZ, fout=300MHZ
apll_pdiv       EQU         6
apll_sdiv       EQU         1
    ENDIF
    IF (apll_clk == clk_400MHZ)
apll_mdiv       EQU         400    ; fvco=800MHZ, fout=400MHZ
apll_pdiv       EQU         6
apll_sdiv       EQU         1
    ENDIF
    IF (apll_clk == clk_532MHZ)
apll_mdiv       EQU         266    ; fvco=1064MHZ, fout=532MHZ
apll_pdiv       EQU         3
apll_sdiv       EQU         1
    ENDIF
    IF (apll_clk == clk_666MHZ)
apll_mdiv       EQU         333    ; fvco=1332MHZ, fout=666MHZ
apll_pdiv       EQU         3
apll_sdiv       EQU         1
    ENDIF

; set clock dividers

mpll_div        EQU         1       ; dout_mpll = mpll_fout/2 = 133M
apll_div        EQU         0       ; aclk = apll_clk
hclk_div        EQU         1       ; ahb_clk = hclkx2/2 = 133M
pclk_div        EQU         3       ; pclk = hclkx2/4 = 66.5M

aclk            EQU         (apll_clk/(apll_div+1))
mclk            EQU         (mpll_clk/(mpll_div+1))
pclk            EQU         (hclkx2/(pclk_div+1))

    IF (syncmode == 1)   ; use apll as memory clock source
        IF (apll_clk > clk_532MHZ)
hclkx2_div      EQU         2       ; hclkx2 = apll_clk/3
        ELSE
            IF ((apll_clk > clk_266MHZ) && (apll_clk <= clk_532MHZ))
            ; arm:ahb:apb = 12:2:1, hclkx2 = apll_clk/3
hclkx2_div      EQU         1       ; hclkx2 = apll_clk/2
            ELSE
hclkx2_div      EQU         0       ; hclkx2 = apll_clk/1
            ENDIF
        ENDIF
hclkx2          EQU         (apll_clk/(hclkx2_div+1))
    ELSE ; use mpll as memory clock source
hclkx2_div      EQU         0       ; hclkx2 = mpll_clk
hclkx2          EQU         (mpll_clk/(hclkx2_div+1))
    ENDIF  ;for (syncmode == 1)


hclk            EQU         (hclkx2/(hclk_div+1))

    IF (eclk == eclk_96MHZ)    ; epll fout 96 MHZ
epll_mdiv       EQU         32
epll_pdiv       EQU         1
epll_sdiv       EQU         2
epll_kdiv       EQU         0
    ENDIF    ; for (eclk == eclk_96MHZ)

    IF (eclk == eclk_84_7MHZ)    ; epll fout 84.66666 MHZ
epll_mdiv       EQU         254
epll_pdiv       EQU         9
epll_sdiv       EQU         2
epll_kdiv       EQU         0
    ENDIF    ; for (eclk == eclk_84_7MHZ)

    IF (eclk == eclk_92MHZ)    ; epll fout 92.16 MHZ
epll_mdiv       EQU         254
epll_pdiv       EQU         9
epll_sdiv       EQU         2
epll_kdiv       EQU         0
    ENDIF    ; for (eclk == eclk_92MHZ)

    MACRO
    mov_pc_lr
    IF ({CONFIG} == 16)
            bx      lr
    ELSE
            mov     pc,lr
    ENDIF
    MEND

    MACRO
    moveq_pc_lr
    IF ({CONFIG} == 16)
            bxeq      lr
    ELSE
            moveq     pc,lr
    ENDIF
    MEND
    END